1. Field of the Invention
The present invention relates to integrated circuit devices. More particularly, the present invention relates to high input/output (I/O) count integrated circuit devices suitable for use in multichip module (MCM) configurations and which incorporate two different types of input/output (I/O) nodes, a first type having high current drive capability for driving off-chip signals and a second type comprising externally accessible internal nodes of the integrated circuit having low current drive capability for driving signals to externally-accessible internal nodes of neighboring integrated circuits on an MCM substrate. The integrated circuit devices may include logic or other function circuit modules and may also include programmable interconnect structures.
2. The Prior Art
Commercial integrated circuits have recently begun to become I/O limited. That is, that a present limitation on integration, other than the die size limitation which restricts the number of active devices disposed upon a substrate, is that I/O requirements of some otherwise integrable circuits have begun to exceed the number of I/O nodes, i.e., external pins which can be provided for a given integrated circuit device. For example, field programmable gate array (FPGA) devices presently have gate densities in the 1K to 8K gate range. I/O capability of these devices is limited by several factors. Commercial packages such as DIP, QFP and Pin Grid array (PGA) rely on wire bonding techniques in which the I/O have to be placed on the periphery of the chip. The periphery of the FPGA chip can support only a limited number of I/O pads dictated by the available peripheral area of the integrated circuit die.
In addition, FPGA products are designed to have I/O buffers capable of driving 50 pF loads normally seen in printed circuit board environments. The power dissipation design requirements of these high-drive I/O buffers constrains the number of I/O nodes possible on any FPGA chip due to power dissipation limits dictated by the package thermal resistance.
Recent applications of reprogrammable FPGAs to emulate high gate count ASICs have shown that available partitioning algorithms for automatically partitioning ASIC designs into FPGAs are constrained mainly by low gate utilization, i.e., an inability to utilize fully the available internal gates on the integrated circuit. This inefficiency results from the relatively low I/O capability of commercial FPGAs. For example, a 3090 integrated circuit manufactured by Xilinx of San Jose, California has 140 I/O nodes and can be used to map 250 to 500 gates only with automatic partition algorithms. However the Xilinx 3090 FPGA device can accommodate more than 3,000 gates. This plainly represents an inefficiency of about a factor of 10.
It would be very desirable to provide an integrated circuit architecture having about 10 times the I/O capability of presently available commercial ICs (a few hundreds to a few thousands of I/O nodes). This will enable building, for example, reprogrammable ASIC devices having gate counts greater than 10,000, i.e., 100,000 gates, more economically and at a much higher performance.